The present invention disclosed herein relates to a semiconductor memory device and more particularly, to a flash memory device and control method of a flash memory device.
Semiconductor memory devices are generally classified as volatile or nonvolatile. Advantages of volatile semiconductor memory devices include rapid read and write speeds, and disadvantages include losing stored contents when power is removed. In comparison, nonvolatile semiconductor memory devices are able to retain stored contents, even when power is removed. Therefore, nonvolatile semiconductor memory devices are used for applications that require contents to be stored regardless of whether power is continually applied. Nonvolatile semiconductor memory devices include, for example, mask read-only memory (MROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and the like.
Some non-volatile memories, however, such as MROM, PROM and EPROM, can not to be erased or written to by a system itself, so it is difficult for general users to update stored contents. On the other hand, EEPROM is capable of being electrically erased or written. Accordingly, EEPROM applications have widened to auxiliary memories and system programming requiring continuous updates (e.g., flash EEPROM). Flash EEPROM exhibits higher degree of integration than conventional EEPROM, and is therefore particularly suited for large auxiliary memory applications. A NAND-type flash EEPROM (hereinafter, referred to as a NAND flash memory device) is more highly integrated than other types of flash EEPROMs.
In general, a flash memory device is an integrated circuit configured to store information and to read stored information, as needed. A flash memory device may include multiple memory cells having re-writing capabilities. Each of the memory cells may store single-bit data or multi-bit data. A flash memory device may have increased functionality due to high integration, large volume, and the like. Although this trend decreases minimum feature size, it may increase complexity and thus reduce chip yield.
Therefore, a flash memory device may include redundant memory cells for replacing defective memory cells, as well as means for switching an address of a defective memory cell to an address of a redundant memory cell. If a bad block having defective memory cells is detected during testing, a row decoder may be set so that the bad block is not selected. The row decoder may include a block decoder for selecting rows in a block unit. The block decoder includes a fuse or a latch circuit that is set to interrupt accessing a bad block.
FIGS. 1A and 1B are circuit diagrams showing conventional block decoders configured to interrupt access to a bad block. FIG. 1A shows an example of a block decoder configured such that a bad block is processed based on whether a fuse 12 is programmed. FIG. 1B shows an example of a block decoder configured such that a bad block is processed based on information stored in a latch 22.
Referring to FIG. 1A, a memory block is treated as a bad block by cutting the fuse 12 of block decoder 10. In this case, although block select signals Pi, Qi and Ri for selecting the memory block all are high, an output signal of NAND gate 11 is not transferred to node N1 when the fuse 12 is cut. Accordingly, the node N1 has a high level and a node N2 has a low level. As a result, selection of the bad block is interrupted, since a string select line SSL is grounded and a block word line BWL is set to a low level.
Referring to FIG. 1B, data indicating a bad block or a normal block may be stored in the latch 22 of block decoder 20. Logic “1” may be stored in the latch 22 to indicate a bad block and logic “0” may be stored in the latch 22 to indicate a normal block. When logic “1” is stored in the latch 22 of the block decoder 20, the logic “1” is sent to an input terminal of NOR gate 23. Node N3 is therefore set to a low level, regardless of the values of block select signals Pi, Qi and Ri.
As illustrated in FIGS. 1A and 1B, conventional block decoders include a fuse or a latch circuit for managing a bad block. However, such block decoder configurations increase complexity of the memory device and size of the row decoder. When a block decoder includes a fuse, the number of bad blocks may increase due to instability of fuse programming. When a block decoder includes a latch, an error may arise in an initial operation during which bad block information is stored in the latch. A flash memory device may further include means for writing data in a latch incorporated in the row decoder. Accordingly, a flash memory device is needed that is capable of managing bad blocks by means of a simple row decoder structure.